Technical Field
This disclosure relates generally to a bit-cell voltage distribution system.
Description of the Related Art
In some designs, bit-cells of memory devices may be subject to various forms of unstable read errors. One form of unstable read error at a bit-cell, known as a read disturb error, occurs when a word line is connected to an operating voltage prior to a bit-cell being connected to the operating voltage. If the word line is connected to the operating voltage prior to the bit-cell being connected to the operating voltage, a bit line may be connected to a data value of the bit-cell while the bit-cell is operating using a retention voltage. As a result, a precharge voltage of the bit line may activate a portion of the bit-cell, destroying the data value. Read disturb errors may be made worse by process variations, which may make signals used to connect the word line to the operating voltage propagate faster than signals used to connect the bit-cell to the operating voltage. Additionally, a smaller retention voltage at the bit-cell may similarly make read disturb errors worse (e.g., because the bit-cell make take longer to reach a voltage where the bit line does not destroy the data value).
One way to prevent read disturb errors is to time wakeup signals such that the word line is connected to the operating voltage a particular amount of time (e.g., 500 picoseconds) after the bit-cell has been connected to the operating voltage. However, safety margins associated with such a process may, in many cases, result in additional delay.